The integration of logic arrays and memory arrays, such as dynamic random access memory (DRAM), within a single semiconductor structure continues to increase every year. This integration of logic and DRAMs to achieve dense high performance embedded dynamic random access memory (EDRAM) technology presents two basic tradeoffs: either a dense memory cell array with slower logic can be achieved, or an inefficient, larger memory cell array with faster logic is possible.
In the dense memory array with slower logic design, referred in the industry as merged DRAM logic (MDL), a high speed dual work function (DWF) logic support design is traded for a conventional DRAM (CDRAM) based single work function (SWF) design. A SWF design comprises relatively “slower” logic with a capped gate electrode leading to a very dense memory array design employing a borderless pitch array, i.e., an array that is borderless between the gate (word-line) and bit-line contact. The MDL design typically has a logic core performance that is 20–30% slower than the alternative large cell memory array and fast logic approach.
In the large cell memory array and fast logic approach, referred to in the industry as merged logic DRAM (MLD), a densely packed memory array cell is traded for the high speed dual work function (DWF) logic. A borderless array bit-line contact is given up, and the array cell efficiency is decreased by at least 30% compared with the above-described dense array and slower logic implementation (i.e., MDL design).
In view of the above tradeoffs, there exists a need in the art for a structure which integrates dual work function logic technology with a borderless contact to achieve MLD performance and MDL array efficiency, and which results in a cost effective, high performance embedded DRAM structure and process.